MIME-Version: 1.0 Content-Type: multipart/related; boundary="----=_NextPart_01C5677F.91E1D090" This document is a Web archive file. If you are seeing this message, this means your browser or editor doesn't support Web archive files. For more information on the Web archive format, go to http://officeupdate.microsoft.com/office/webarchive.htm ------=_NextPart_01C5677F.91E1D090 Content-Location: file:///C:/4E691D13/POST-BeepCodes.htm Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset="us-ascii" computer POST / Beep Codes

computer POST / Beep Codes.

POST ABCs

     The computer POST (Power = On Self Test) which tests the computer insuring that it meets the necessary system requirements before booting up. If the computer fails the POST the computer then returns a beep code indicating what is causing the computer n= ot to post the POST. Generally if the computer POSTs properly you will receive a single beep (with some computer BIOS manufacturers it may beep twice).

THE POST TEST

Each time the computer boots up the computer must pas= t the POST. The following is the procedure of the POST:

1.&n= bsp;     The first step o= f POST is the testing of the Power Supply to ensure that it is turned on and that = it releases its reset signal.

 

2.&n= bsp;     CPU must exit the reset status mode and thereafter be able to execute instructions.

 

3.&n= bsp;     BIOS must be have readable.

 

4.&n= bsp;     BIOS checksum mu= st be valid, meaning that it must be readable.

 

5.&n= bsp;     CMOS be accessib= le for reading.

 

6.&n= bsp;     CMOS checksum mu= st be valid, meaning that it must be readable.

 

7.&n= bsp;     CPU must be able= to read all forms of memory such as the memory controller, memory bus, and mem= ory module.

 

8.&n= bsp;     The first 64KB of memory must be operational and have the capability to be read and written to and from, and capable of containing the POST code.

 

9.&n= bsp;     I/O bus / contro= ller must be accessible.

 

10.&= nbsp; I/O bus must be able to write / read from the video subsystem and be able to read all video RAM..

If the computer does not pass any= of the above tests your computer will receive an irregular POST. An irregular POST is a beep code which is different = from the standard which can be either no beeps at all= or a combination of different beeps indicating what is causing the computer not = to past the POST.

 

=  

 

AMI BIOS BEEP CODES

The following are AMI BIOS Beep Codes that can occur. However because of the wide variety of different computer manufacturers wit= h this BIOS the beep codes may vary.

Beep Code<= span style=3D'color:black'>

Descriptions

1 short

DRAM refresh failure

2 short

Parity circuit failure

3 short

Base 64K RAM failure

4 short

System timer failure

5 short

Process failure

6 short

Keyboard controller Gate= A20 error

7 short

Virtual mode exception e= rror

8 short

Display memory Read/Writ= e test failure

9 short

ROM BIOS checksum failur= e

10 short

CMOS shutdown Read/Write= error

11 short

Cache Memory error<= /o:p>

1 long, 3 short

Conventional/Extended me= mory failure

1 long, 8 short

Display/Retrace test fai= led

AWARD BIOS BEEP CODES=

The following are Award BIOS Beep Codes that can occu= r. However because of the wide variety of different computer manufacturers wit= h this BIOS the beep codes may vary.

Beep Code<= span style=3D'color:black'>

Description

1 long, 2 short

Indicates a video error = has occurred and the BIOS cannot initialize the video screen to display any additional information

Any other beep(s)

RAM problem.

If any other correctable hardware= issues the BIOS will display a message.<= o:p>

 

IBM BIOS

The following are IBM BIOS Beep Codes that can occur. However because of the wide variety of models shipping with this BIOS the beep codes may vary.

Beep Code<= span style=3D'color:black'>

Description

No Beeps

No Power, Loose Card, or= Short.

1 Short Beep<= /span>

Normal POST, computer is= ok.

2 Short Beep<= /span>

POST error, review scree= n for error code.

Continuous Beep

No Power, Loose Card, or= Short.

Repeating Short Beep

No Power, Loose Card, or= Short.

One Long and one Short B= eep

Motherboard issue.<= /o:p>

One Long and Two short B= eeps

Video (Mono/CGA Display Circuitry) issue.

One Long and Three Short= Beeps.

Video (EGA) Display Circ= uitry.

Three Long Beeps

Keyboard / Keyboard card= error.

One Beep, Blank or Incor= rect Display

Video Display Circuitry.=

MACINTOSH STARTUP TONES

TONES

ERROR

Error Tone. (two sets of different tones)

Problem with logic board= or SCSI bus.

Startup tone, drive spin= s, no video

Problem with video contr= oller.

Powers on, no tone.=

Logic board problem.

High Tone, four higher t= ones.

Problem with SIMM.<= /o:p>

PHOENIX= BIOS BEEP CODES

The following is for PHOENIX BIOS Q3.07 OR 4.X <= /o:p>

Beep Code<= span style=3D'color:black'>

Description / What to= Check

1-1-1-3

Verify Real Mode.

1-1-2-1

Get CPU type.=

1-1-2-3

Initialize system hardwa= re.

1-1-3-1

Initialize chipset regis= ters with initial POST values.

1-1-3-2

Set in POST flag.

1-1-3-3

Initialize CPU registers= .

1-1-4-1

Initialize cache to init= ial POST values.

1-1-4-3

Initialize I/O.

1-2-1-1

Initialize Power Managem= ent.

1-2-1-2

Load alternate registers= with initial POST values.

1-2-1-3

Jump to UserPatch0.=

1-2-2-1

Initialize keyboard cont= roller.

1-2-2-3

BIOS ROM checksum.<= /o:p>

1-2-3-1

8254 timer initializatio= n.

1-2-3-3

8237 DMA controller initialization.

1-2-4-1

Reset Programmable Inter= rupt Controller.

1-3-1-1

Test DRAM refresh.<= /o:p>

1-3-1-3

Test 8742 Keyboard Contr= oller.

1-3-2-1

Set ES segment to regist= er to 4 GB.

1-3-3-1

28 = Autosize DRAM.

1-3-3-3

Clear 512K base RAM.

1-3-4-1

Test 512 base address li= nes.

1-3-4-3

Test 512K base memory.

1-4-1-3

Test CPU bus-clock frequ= ency.

1-4-2-4

Reinitialize the chipset= .

1-4-3-1

Shadow system BIOS ROM.<= o:p>

1-4-3-2

Reinitialize the cache.<= o:p>

1-4-3-3

Aut= osize cache.

1-4-4-1

Configure advanced chips= et registers.

1-4-4-2

Load alternate registers= with CMOS values.

2-1-1-1

Set Initial CPU speed.

2-1-1-3

Initialize interrupt vec= tors.

2-1-2-1

Initialize BIOS interrup= ts.

2-1-2-3

Check ROM copyright noti= ce.

2-1-2-4

Initialize manager for P= CI Options ROMs.

2-1-3-1

Check video configuration against CMOS.

2-1-3-2

Initialize PCI bus and d= evices.

2-1-3-3

Initialize all video ada= pters in system.

2-1-4-1

Shadow video BIOS ROM.

2-1-4-3

Display copyright notice= .

2-2-1-1

Display CPU type and spe= ed.

2-2-1-3

Test keyboard.

2-2-2-1

Set key click if enabled= .

2-2-2-3

56 Enable keyboard.=

2-2-3-1

Test for unexpected inte= rrupts.

2-2-3-3

Display prompt "Pre= ss F2 to enter SETUP".

2-2-4-1

Test RAM between 512 and= 640k.

2-3-1-1

Test expanded memory.

2-3-1-3

Test extended memory add= ress lines.

2-3-2-1

Jump to UserPatch1.=

2-3-2-3

Configure advanced cache registers.

2-3-3-1

Enable external and CPU = caches.

2-3-3-3

Display external cache s= ize.

2-3-4-1

Display shadow message.<= o:p>

2-3-4-3

Display non-disposable s= egments.

2-4-1-1

Display error messages.<= o:p>

2-4-1-3

Check for configuration = errors.

2-4-2-1

Test real-time clock.

2-4-2-3

Check for keyboard error= s

2-4-4-1

Set up hardware interrup= ts vectors.

2-4-4-3

Test coprocessor if pres= ent.

3-1-1-1

Disable onboard I/O port= s.

3-1-1-3

Detect and install exter= nal RS232 ports.

3-1-2-1

Detect and install exter= nal parallel ports.

3-1-2-3

Re-initialize onboard I/= O ports.

3-1-3-1

Initialize BIOS Data Are= a.

3-1-3-3

Initialize Extended BIOS= Data Area.

3-1-4-1

Initialize floppy contro= ller.

3-2-1-1

Initialize hard-disk con= troller.

3-2-1-2

Initialize local-bus har= d-disk controller.

3-2-1-3

Jump to UserPatch2.=

3-2-2-1

Disable A20 address line= .

3-2-2-3

Clear huge ES segment re= gister.

3-2-3-1

Search for option ROMs.<= o:p>

3-2-3-3

Shadow option ROMs.=

3-2-4-1

Set up Power Management.=

3-2-4-3

Enable hardware interrup= ts.

3-3-1-1

Set time of day.

3-3-1-3

Check key lock.

3-3-3-1

Erase F2 prompt.

3-3-3-3

Scan for F2 key stroke.<= o:p>

3-3-4-1

Enter SETUP.<= /span>

3-3-4-3

Clear in-POST flag.=

3-4-1-1

Check for errors

3-4-1-3

POST done--prepare to bo= ot operating system.

3-4-2-1

One beep.

3-4-2-3

Check password (optional= ).

3-4-3-1

Clear global descriptor = table.

3-4-4-1

Clear parity checkers.

3-4-4-3

Clear screen (optional).=

3-4-4-4

Check virus and backup reminders.

4-1-1-1

Try to boot with INT 19.=

4-2-1-1

Interrupt handler error.=

4-2-1-3

Unknown interrupt error.=

4-2-2-1

Pending interrupt error.=

4-2-2-3

Initialize option ROM er= ror.

4-2-3-1

Shutdown error.

4-2-3-3

Extended Block Move.

4-2-4-1

Shutdown 10 error.<= /o:p>

4-3-1-3

Initialize the chipset.<= o:p>

4-3-1-4

Initialize refresh count= er.

4-3-2-1

Check for Forced Flash.<= o:p>

4-3-2-2

Check HW status of ROM.

4-3-2-3

BIOS ROM is OK.

4-3-2-4

Do a complete RAM test.<= o:p>

4-3-3-1

Do OEM initialization.

4-3-3-2

Initialize interrupt con= troller.

4-3-3-3

Read in bootstrap code.<= o:p>

4-3-3-4

Initialize all vectors.<= o:p>

4-3-4-1

Boot the Flash program.<= o:p>

4-3-4-2

Initialize the boot devi= ce.

4-3-4-3

Boot code was read OK.

 

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